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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
1mo
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Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
5d
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
1mo
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
1mo
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
2mo
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Staff Design Engineer
San Jose, California, United States
$145k-$246k/yr OnsiteFull Time
7+ YOEBachelor's in Computer or Electrical Engineering; 7+ years digital circuit design; RTL and gate-level verification; collaboration across multi-functional teams.
RTL, Verilog, Gate-level verification
6d
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Senior Design Engineer
San Jose, California, United States
$116k-$198k/yr OnsiteFull Time
5+ YOEBachelor's in Computer or Electrical Engineering,5+ years digital circuit design experience,RTL and gate-level verification,Verilog proficiency,ability to meet performance/area/power targets.
RTL, Verilog, AI tools
3w
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Product Development Engineer
San Jose, California, United States
$106k-$154k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in Electrical Engineering (or related) with 5+ years industry experience in IC design/test, DFT/ATPG/MBIST/IJTAG/JTAG, RTL design/synthesis/verification, scripting (Python/Perl/TCL), and semiconductor manufacturing test.
Python, Perl, TCL, ATPG, MBIST, IJTAG, JTAG, RTL, Secure Device Manager (SDM)
1mo
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Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
1d
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3D Stacked DRAM-on-Logic Design Engineer
San Jose, California, United States
$150k-$260k/yr OnsiteFull Time
5+ YOEBachelor's in EE,5+ years experience in digital IP/SoC and RTL design for 3D-stacked DRAM,experience with Verilog/VHDL,memory controllers,BIST/DFT/DFD,and strong English communication.
Verilog, VHDL, RTL
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Digital Design Engineer - New College Grad
San Jose, California, United States
$99k-$183k/yr HybridFull Time
Master's degree in EE or related field; experience with RTL coding, Verilog models, and analog/digital design; test support and chip bring-up; strong communication and team skills.
Verilog, RTL, Simulations, I2C, SPI, AHB, APB, Bench testing, ATE testing
1w
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Design Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in Electrical/Computer Engineering (or equivalent), 3+ years SystemVerilog RTL design experience, strong digital design fundamentals, power/timing-aware practices, simulation debug, and scripting in Python/Perl/TCL.
SystemVerilog, Python, Perl, TCL, UVM, SVA
1mo
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Physical Design Engineer
San Jose or Austin
$165k-$241k/yr OnsiteFull Time
1+ YOEBachelor’s/Master’s/PhD in Electrical or Computer Engineering with ASIC RTL-to-GDSII experience for advanced nodes; experience with Innovus, Tempus/PrimeTime, Redhawk/Voltus, Calibre/Pegasus, Python, and STA.
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, Tweaker, Python
1w
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Application Engineer, Customer Engagement
San Jose, California, United States
$152k-$191k/yr HybridFull Time
3+ YOEMaster's in EE/CE or related, 3+ years engineering experience, System Verilog RTL, formal verification, Jasper tool experience, SAT solvers, STA, strong communication and mentoring skills.
Jasper, Jasper SEC, Jasper LEC, SAT solvers, System Verilog, Electronic Design Automation (EDA), Static Timing Analysis (STA)
1mo
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Applications Engineer
San Jose, California, United States
$130k-$350k/yr OnsiteFull Time
Experience in RTL design/verification, Verilog/SystemVerilog and verification methodologies (UVM); BS/MS in EE/CE/CS; strong customer-facing, presentation, and problem-solving skills.
Synopsys VCS, Cadence Xcelium, Siemens Questa, Verilog, SystemVerilog, UVM, Python, Tcl, Shell
3w
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Principal Design Engineer
San Jose or Cary
$137k-$254k/yr OnsiteFull Time
1+ YOEBS/MS/PhD in Electrical Engineering with 7/5/1+ years respectively; experience with Cadence Innovus/Tempus/QRC/Voltus/Pegasus and Palladium/Protium; Linux and Shell/Perl/TCL scripting; RTL synthesis, floorplanning, timing closure, IR drop, and industry interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).
Innovus, Tempus, QRC, Voltus, Pegasus, Palladium, Protium, Linux, Shell, Perl, TCL
2mo
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FPGA Engineer (CA, San Jose)
San Jose, California, United States
HybridFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience in FPGA design and verification, proficiency in RTL/C/C++, Python; familiarity with VHDL/Verilog, hardware security, IP core development, and FPGA tools.
C, C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Altera, Versal, Stratix, Avalon, AXI, ACE, IP cores, cocotb, pyuvm
1w
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Senior FPGA Design Engineer,( Nextest, San Jose, CA)
San Jose, California, United States
$170k-$273k/yr OnsiteFull Time
8+ YOEB.S. or M.S. in Electrical Engineering, 8+ years relevant experience, RTL/Verilog, FPGA transceiver and timing experience, C/C++, EM/FPGA tool flow familiarity, lab equipment experience.
C, C++, Linux, Windows, Verilog HDL, Intel FPGA tool flows, Xilinx FPGA tool flows, UVM, ATE
2mo
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Senior Digital Design Engineer, IP and Methodology
San Jose, California, United States
$135k-$195k/yr OnsiteFull Time
3+ YOEBachelor's degree in Electrical Engineering; 3+ years in SoC/silicon; RTL/systemVerilog; CPU subsystem or embedded processor integration; security fundamentals in silicon; clocking, CDC, RDC; SystemVerilog and Python in production.
SystemVerilog, Python, Synopsys, Cadence, UVM
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