24 rtl jobs at 13 companies in Santa Rosa, CA
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
1w
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Core Performance Architect
Santa Clara or Hsinchu or Austin or Berkeley
$179k-$219k/yr OnsiteFull Time
3+ YOEMS in Computer Science/Computer Architecture,3+ years in high-performance processor development,experience with RTL/FPGA and performance analysis,ability to deliver HW/SW products.
RTL, FPGA, Integrated Logic Analyzer
3mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
3w
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Director, Product Engineering Practice Specialist (Semiconductor)
San Francisco or Austin
$200k-$280k/yr OnsiteFull Time
15+ YOE15+ years in semiconductor/product engineering with deep expertise in silicon, SoC, RTL, verification, validation, embedded software, solutioning, and client advisory for large-scale engineering transformations.
Synopsys, Cadence, Siemens, UVM, SystemVerilog, Linux, C++, RISC-V
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1w
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Senior Consultant
San Francisco, California, United States
OnsiteFull Time
5+ YOERequires 5–20 years in hardware-assisted verification, Linux boot and kernel debugging, digital design, emulation, PCIe Gen6, Python, C or Perl scripting, and SystemVerilog RTL coding.
AI, High Performance Computing (HPC), SystemVerilog, Linux, PCIe, HBM, JTAG, UART, Virtual IXIA, ZeBu, Palladium, Veloce, HAPS, Protium, ProFPGA, Python, C, Perl, UVM, C++, SystemC, PCIe Gen6, QEMU
4w
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Senior Product Manager - Platform
San Francisco or New York City
$200k-$225k/yr OnsiteFull Time
5+ YOE5+ years product management with platform/infrastructure ownership, experience with enterprise healthcare integrations (EHRs/RTLS), strong technical judgment, data-driven decision making, and cross-functional collaboration.
EHRs, RTLS, APIs
1d
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Sr. FPGA Design & Verification Engineer
San Francisco or Oakland
$137k-$188k/yr HybridFull Time
2+ YOERequires a master's degree plus 2+ years, bachelor's degree plus 3+ years, or equivalent experience; FPGA/RTL design, VHDL, Verilog, SystemVerilog, simulation, debugging, scripting, and laboratory equipment experience.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers, FPGA
1d
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Sr. FPGA Design & Verification Engineer
San Francisco, California, United States
$137k-$188k/yr HybridFull Time
2+ YOEMaster's degree plus 2+ years or bachelor's degree plus 3+ years of engineering experience; expertise in FPGA and RTL design, VHDL, Verilog, SystemVerilog, simulation, verification, debugging, laboratory equipment, and scripting.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers
1w
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Senior Research Scientist, Superconducting Digital Electronics, Quantum AI
Goleta or Cambridge or Mountain View or Seattle or San Francisco or Washington
$174k-$252k/yr OnsiteFull Time
Master's in EE/Physics or equivalent, experience with superconducting logic and tape-out, published research, B.S. preferred PhD, experience in full digital design flow and low-temperature measurements preferred.
RTL, computer-aided design tools
3d
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Silicon Architect
San Francisco, California, United States
$198k-$233k/yr HybridFull Time
10+ YOE10+ years in semiconductor definition, architecture, SoC/ASIC development, or system architecture for high-volume consumer electronics; expertise in low-power design, semiconductor flows, vendors, and technical leadership.
SoC, ASIC, RTL, CPUs, NPUs, DSPs
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Member of Technical Staff - Low Level & Kernels Capabilities
San Francisco or Toronto or Seattle
$200k-$350k/yr OnsiteFull Time
Experienced low-level systems engineer fluent in C/C++/CUDA and Python, kernel and kernel-optimization experience, hardware-aware coding, familiarity with LLMs, and ability to design robust, ungameable RL environments.
C, C++, CUDA, Python, assembly, cuBLAS, FFTW, OpenSSL, FPGA, RISC-V, SIMD, AVX, TPU, RTL, HDL, HLS, MLIR, LLVM, Mojo, Triton, gem5, Lean, Coq, SMT
1w
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Director, Product Engineering Practice Specialist (Semiconductor)
San Francisco or Austin or Nevada
$200k-$280k/yr OnsiteFull Time
15+ YOE15+ years in semiconductor or product engineering, silicon design, embedded systems, or consulting; expertise in semiconductor technologies, solutioning, architecture, consulting, practice leadership, and executive advisory.
ASIC, SoC, RTL, UVM, SystemVerilog, DFT, STA, CPU, GPU, TPU, AI Accelerators, Networking ASICs, HBM, C, C++, Linux, RTOS, FPGA, Synopsys, Cadence, Siemens EDA, RISC-V, AI/ML, HPC
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