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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
2d
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HBM SoC RTL Design Engineer
Folsom, California, United States
$121k-$247k/yr OnsiteFull Time
3+ YOE3+ years SoC/RTL design experience, proficiency in SystemVerilog/Verilog, RTL-to-GDS flow knowledge, familiarity with EDA toolchains, scripting (Python/TCL/Perl/shell), and SoC integration skills.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, shell, Palladium, Veloce, Zebu
2mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
2mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
2mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
2mo
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Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
1mo
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
2mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
2mo
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Staff Electrical Engineer – FPGA / MPSoC Systems & Digital Signal Processing
San Leandro, California, United States
$160k-$240k/yr OnsiteFull Time
5+ YOE5+ years in FPGA/MPSoC design, DSP for real-time systems, MATLAB/Python, HDL/RTL, and hardware-software integration.
HDL/RTL, MATLAB, Python, FPGA, MPSoC, Digital Signal Processing, Schematic reading, Oscilloscopes, Logic Analyzers
2w
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Director, Product Engineering Practice Specialist (Semiconductor)
San Francisco or Austin
$200k-$280k/yr OnsiteFull Time
15+ YOE15+ years in semiconductor/product engineering with deep expertise in silicon, SoC, RTL, verification, validation, embedded software, solutioning, and client advisory for large-scale engineering transformations.
Synopsys, Cadence, Siemens, UVM, SystemVerilog, Linux, C++, RISC-V
1w
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Principal Engineer, SOC Design
Folsom, California, United States
$199k-$319k/yr OnsiteFull Time
15+ YOEExtensive SoC architecture and RTL development experience with modern DRAM technologies, verification/debugging skills, FPGA prototyping or silicon bring-up experience, and strong technical leadership.
SystemVerilog, Verilog, FPGA
3w
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
2w
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
2mo
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Mixed Signal Logic Design Engineer
Folsom or San Jose or Santa Clara
$122k-$232k/yr OnsiteFull Time
4+ YOEBachelor's with 4+ years or Master's with 3+ years or PhD with 1+ year in CS/CE/EE; 2+ years RTL design SystemVerilog/Verilog; mixed-signal, UPF, clock gating; VCS/Verdi; FE tools; no visa sponsorship.
SystemVerilog, Verilog, VCS, Verdi, UPF, Lint, CDC, RDC, Synthesis, Voltage Domain Crossings, DDR, LPDDR, VSCode, Git
1mo
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Senior Engineer Space Electronics
Pleasanton, California, United States
$142k-$186k/yr OnsiteFull Time
3+ YOEBachelor's in EE (or related) with 6+ yrs or Master's with 3+ yrs; 3+ yrs space/LEO electronics design; experience with power, analog, mixed‑signal, radiation testing/mitigation; LTSpice proficiency; high‑speed PCB design and lab test equipment experience; must be U.S. Person.
LTSpice, FPGA, MCU, RTL, AS9100, Oscilloscope, VNA, Spectrum Analyzer, Power Supply, Function Generator, DVM
1mo
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Member of Technical Staff - Low Level & Kernels Capabilities
San Francisco or Toronto or Seattle
$200k-$350k/yr OnsiteFull Time
Experienced low-level systems engineer fluent in C/C++/CUDA and Python, kernel and kernel-optimization experience, hardware-aware coding, familiarity with LLMs, and ability to design robust, ungameable RL environments.
C, C++, CUDA, Python, assembly, cuBLAS, FFTW, OpenSSL, FPGA, RISC-V, SIMD, AVX, TPU, RTL, HDL, HLS, MLIR, LLVM, Mojo, Triton, gem5, Lean, Coq, SMT
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