1mo
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
4w
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
2mo
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
2mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
2mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
2mo
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PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |
Bay Area, California, United States
OnsiteFull Time
15+ YOE15+ years ASIC CAD, design methodology, and physical design; multi-node, multi-foundry platform deployments; R2G across major nodes; UPF/CPF flows; clocking and chiplet/2.5D methods.
EDA tools, RTL-to-GDSII
1mo
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Staff Silicon Validation Engineer
Palo Alto, California, United States
$186k-$232k/yr OnsiteFull Time
Bachelor's degree in EE/CSE or related, proficiency in C/C++, Python and Linux shell, experience with SoC/FPGA validation preferred (AMD Petalinux, RTL), strong analytical and communication skills.
C, C++, Python, Linux shell, AMD Petalinux, FPGA, RTL
1mo
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
2mo
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Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
2mo
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Staff Electrical Engineer – FPGA / MPSoC Systems & Digital Signal Processing
San Leandro, California, United States
$160k-$240k/yr OnsiteFull Time
5+ YOE5+ years in FPGA/MPSoC design, DSP for real-time systems, MATLAB/Python, HDL/RTL, and hardware-software integration.
HDL/RTL, MATLAB, Python, FPGA, MPSoC, Digital Signal Processing, Schematic reading, Oscilloscopes, Logic Analyzers
2mo
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Senior DFT Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior DFT Engineer with 8+ years in design-for-test for complex digital ASICs/SoCs; expertise with DFT tools; RTL/ASIC test optimization.
Verilog, SystemVerilog, UVM, VHDL, Tcl, Python, Perl, Synopsys DFT Compiler, Tessent, DFTMAX, MBIST, JTAG, ATPG
1w
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Ricursive at DAC 2026 — Introduce Yourself
Palo Alto, California, United States
OnsiteFull Time
Open invitation to submit a resume and state interest for roles in EDA algorithms, design verification, RTL, LLM modeling/infrastructure; on-site in Palo Alto.
Gemini, Claude, Grok, TPUs
2w
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Director, Product Engineering Practice Specialist (Semiconductor)
San Francisco or Austin
$200k-$280k/yr OnsiteFull Time
15+ YOE15+ years in semiconductor/product engineering with deep expertise in silicon, SoC, RTL, verification, validation, embedded software, solutioning, and client advisory for large-scale engineering transformations.
Synopsys, Cadence, Siemens, UVM, SystemVerilog, Linux, C++, RISC-V
2d
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Principal DFT Engineer (Silicon Engineering)
Palo Alto, California, United States
$220k-$355k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE/CS,10+ years ASIC and DFT experience including scan insertion, ATPG, and post-silicon validation; leadership and RTL/verification skills preferred.
Siemens Tessent, ATPG, Perl, Python, Tcl, C+, Verilog, SystemVerilog, UPF, SDF, ATE
3w
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
2w
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
2w
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FPGA Software
San Carlos, California, United States
$150k-$200k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years FPGA/RTL design experience,proficiency in SystemVerilog/Verilog,Vivado/Vitis/Petalinux,ARM SoC platforms,DDR/DMA design,C/C++/Python for bring-up.
SystemVerilog, Verilog, Zynq UltraScale+, Versal, Cyclone 10, Vivado, Vitis, Petalinux, Quartus, Questa, ModelSim, Xcelium, Verilator, UVM, C, C++, Python, TCL, OpenBMC, Redfish, IPMI
1mo
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Senior Engineer Space Electronics
Pleasanton, California, United States
$142k-$186k/yr OnsiteFull Time
3+ YOEBachelor's in EE (or related) with 6+ yrs or Master's with 3+ yrs; 3+ yrs space/LEO electronics design; experience with power, analog, mixed‑signal, radiation testing/mitigation; LTSpice proficiency; high‑speed PCB design and lab test equipment experience; must be U.S. Person.
LTSpice, FPGA, MCU, RTL, AS9100, Oscilloscope, VNA, Spectrum Analyzer, Power Supply, Function Generator, DVM
1d
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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