1w
Save
Mark Applied
Hide
Principal Engineer, SOC Integration
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
18+ YOEBS/MS in Computer/Electrical Engineering or CS with extensive ASIC/SoC experience (18+ years MS or 20+ years BS). Hands-on ASIC tape-out, commercial IPs (UCIe, CPU, DDR, Ethernet), SoC synthesis/timing/DFT, AMBA/ARM experience.
UCIe, ARM, DDR, Ethernet, AMBA, DFT, CDC
1w
Save
Mark Applied
Hide
SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
2w
Save
Mark Applied
Hide
SoC QoS/Fabric Performance Engineer, Platform Architecture
Cupertino, California, United States
OnsiteFull Time
Experienced SoC performance engineer to work with hardware and software teams to shape SoC architecture and develop on-chip interconnect and memory QoS features.
1mo
Save
Mark Applied
Hide
SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
1mo
Save
Mark Applied
Hide
SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
2mo
Save
Mark Applied
Hide
Sr. Principal Engineer, SoC Architect
San Jose, California, United States
$250k-$304k/yr OnsiteFull Time
15+ YOE15+ years in SoC/system architecture; strong high-speed I/O and interconnect knowledge; leadership, cross-functional collaboration.
PCIe, PCIe Gen5, PCIe Gen6, CXL/UCIe, HBM, SerDes, Ethernet, USB, Memory interconnect, Interconnect
2mo
Save
Mark Applied
Hide
SoC Architect
San Jose or United States
$175k-$350k/yr HybridFull Time
18+ YOEBachelor's/Master's/PhD in EE/Computer Engineering or related; 18+ years in SoC/system architecture; expertise in high-speed IO, data movement, performance modeling, and cross-functional collaboration.
UCIe, PCIe, CXL, UALink, ESUN, Ethernet
1mo
Save
Mark Applied
Hide
SoC Architect
Santa Clara, California, United States
$175k-$265k/yr HybridFull Time
d-Matrix: Develops high-performance semiconductor chips for generative AI inference.
5+ YOEMS in CS/ECE or related with 5+ years in SoC/compute architecture; expert in AI SoC architecture, performance modeling, ML (transformer/CNN/RNN), workload analysis; strong Python; C/C++ preferred; leadership in architecture delivery.
Python, C, C++
3mo
Save
Mark Applied
Hide
Senior Staff SoC Design Engineer
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEBachelor's in CS/EE with 5-10 years; or Master's/PhD with 3-5 years; strong SystemVerilog RTL; SoC integration; AMBA AXI; scripting (Python/Tcl).
SystemVerilog, AMBA AXI, Python, Tcl, Synthesis, CDC/RDC, UCIe, UALink
1mo
Save
Mark Applied
Hide
SoC Verification Lead
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
15+ YOE15+ years of ASIC/SoC functional verification experience; Bachelor's/Master's in EE/CE or equivalent; proficiency in SystemVerilog, UVM, C/C++; experience leading verification to tape-out and managing verification plans, schedules, and risk.
SystemVerilog, UVM, C, C++, EDA
1d
Save
Mark Applied
Hide
Datacenter Compute SoC Architect
San Jose or San Diego or Portland or Austin
$211k-$356k/yr OnsiteFull Time
10+ YOE10+ years SoC/compute architecture experience, 3+ years in datacenter/server SoCs; Bachelor’s degree in EE/CE/CS; expertise in CPU/memory/Interconnect, PCIe/CXL, and performance modeling.
C++, SystemC, UCIe, PCIe, CXL, ARM AMBA CHI, AXI
3w
Save
Mark Applied
Hide
SoC Digital Verification Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in a related field,1+ years ASIC/SoC verification experience,mastery of SystemVerilog and UVM,proficiency with simulation/debug tools and Python/Perl/Shell scripting.
SystemVerilog, UVM, VCS, Incisive, Questa, Verdi, Python, Perl, Shell, Palladium, ZeBu, JasperGold, FPGA, ASIC
1mo
Save
Mark Applied
Hide
Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning
Cupertino, California, United States
$183k-$248k/yr OnsiteFull Time
5+ YOEBachelor's in CS/CE/EE with significant experience (BS+6/MS+5/PhD+3). Expertise in chip power analysis, PrimePower/PowerArtist, scripting (Tcl/Perl/Python), EM/IR, thermal, and lab power measurement.
PrimePower, PowerArtist, Tcl, Perl, Python, Make, System verilog, Redhawk, Voltus, Zebu Emulator
2mo
Save
Mark Applied
Hide
Sr. Principal SoC Architect (AI2501)
San Jose, California, United States
$231k-$358k/yr OnsiteFull Time
20+ YOEMS or PhD in EE/CS, 20+ years developing hardware-focused products, 3+ years architecting and tape-out of complex ML SoCs, strong ML/math foundation, HW/SW co-design and industry/publication experience.
2mo
Save
Mark Applied
Hide
SoC Architect, Memory Subsystem
San Jose or Austin
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in computer engineering/memory subsystems; strong knowledge of memory hierarchies, interfaces (DDR/LPDDR/HBM), controllers, caches; experience with PPA optimization; collaboration with software/hardware teams.
DDR memory interfaces, LPDDR, HBM, Memory controllers, Cache subsystems, Cache coherence protocols, Bus protocols (CHI, ACE, AXI), Android ecosystem, Arm architecture, Analysis tools
1w
Save
Mark Applied
Hide
Senior Hardware Engineer - SoC Electrical Failure Analysis (Hybrid)
San Jose, California, United States
$165k-$241k/yr HybridFull Time
Experience in post-silicon validation, SoC failure analysis, power/signal integrity, high-speed interfaces, and driving failure analysis; strong debugging, measurement, and software skills.
Python, C++, Oscilloscopes, VNA, BERT, logic analyzers
2mo
Save
Mark Applied
Hide
FPGA / VLSI Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Design and verify RTL/FPGA, perform FPGA prototyping, and system integration for ASIC/SoC platforms; strong SystemVerilog/Verilog; experience with UVM; VHDL is a plus.
SystemVerilog, Verilog, UVM, VHDL, FPGA, SoC
1d
Save
Mark Applied
Hide
Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
1mo
Save
Mark Applied
Hide
Senior Thermal Engineer
Santa Clara, California, United States
$300k-$655k/yr OnsiteFull Time
5+ YOEMS in Mechanical Engineering required (Ph.D. preferred), 5+ years thermal design experience using Icepak/FloTHERM/SmartCFD, CFD/FEA expertise, liquid cooling and high-power SoC experience, and strong verbal/written communication.
Icepak, FloTHERM, SmartCFD, ProEngineer (PTC Creo), CFD, FEA
3w
Save
Mark Applied
Hide
Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
Explore Jobs
Expand Your Job Search
Top Cities Near Salinas for Soc Engineer
- Soc Engineer jobs in San Jose, CA
- Soc Engineer jobs in Santa Clara, CA
- Soc Engineer jobs in Santa Cruz, CA
- Soc Engineer jobs in Cupertino, CA
- Soc Engineer jobs in Watsonville, CA
- Soc Engineer jobs in Gilroy, CA
- Soc Engineer jobs in Morgan Hill, CA
- Soc Engineer jobs in Campbell, CA
- Soc Engineer jobs in Hollister, CA
- Soc Engineer jobs in Seaside, CA
- Soc Engineer jobs in Saratoga, CA
- Soc Engineer jobs in Los Gatos, CA
- Soc Engineer jobs in Monterey, CA
- Soc Engineer jobs in Soledad, CA
- Soc Engineer jobs in Marina, CA
- Soc Engineer jobs in Greenfield, CA
- Soc Engineer jobs in Live Oak, CA
- Soc Engineer jobs in Pacific Grove, CA
- Soc Engineer jobs in King City, CA
- Soc Engineer jobs in Scotts Valley, CA