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176 verification engineer jobs at 52 companies in Manteca, CA

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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
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1w
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
Lumilens
Lumilens: Designs photonic interconnects for AI supercomputing infrastructure.
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
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Design Verification Engineer
Santa Clara, California, United States
$146k-$250k/yr OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
SystemVerilog/UVM verification expertise; IP/subsystem/SoC verification; testbench development; strong debugging and collaboration.
SystemVerilog, UVM, VCS, Verdi/DVE, Python, Shell, Tcl, Make
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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Alpha Design AI
Alpha Design AI: AI-native EDA platform for semiconductor design and verification.
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
Axiado
Axiado: Creates AI-driven security processors for data center infrastructure.
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
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Verification CAD Engineer
Milpitas, California, United States
$160k-$265k/yr HybridFull Time
Sandisk
SandiskNasdaq: SNDK: Designs and manufactures flash memory and data storage products.
7+ YOEB.S./M.S. in EE/CE/CS,7+ years design verification experience,expert SystemVerilog/UVM and SVA/CDV,advanced Python and Shell skills,Linux and regression farm experience (LSF/NC/Slurm),familiarity with Cadence verification tools.
SystemVerilog, UVM, SVA, Python, Shell, Perl, Xcelium, SimVision, vManager, Verissium, Linux, LSF, NC, Slurm
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2w
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Systems Verification Engineer I
Fremont, California, United States
$106k-$132k/yr OnsiteFull Time
Cytek Biosciences
Cytek BiosciencesNASDAQ: CTKB: Manufacturer of spectral flow cytometry instruments and biological reagents.
0+ YOEBS in Science/Engineering/Math, 0–2 years product development/verification experience for medical devices or IVD, writing requirements, multidisciplinary engineering knowledge, flow cytometry familiarity, experience with system engineering tools.
Helix ALM, Jira, JMP, TestRail, DOORs, SpectroFlo
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3mo
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Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Etched
Etched: Designs specialized AI chips optimized for transformer architectures.
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
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Senior Debug Verification Engineer
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
8+ YOE8+ years ASIC/design verification; SystemVerilog; UVM and formal verification; Linux/Unix scripting with Perl or Python; strong cross-site collaboration.
SystemVerilog, UVM, Formal verification, Linux, Perl, Python, Emulation, JTAG, PCIe, USB
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2mo
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SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
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1mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
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Staff Engineer Verification
San Jose, California, United States
$118k-$162k/yr HybridFull Time
Infineon Technologies
Infineon TechnologiesFrankfurt Stock Exchange: IFX: Designs and manufactures semiconductors for power and IoT systems.
1+ YOE1+ years experience in high-speed SI/PI and EMC; degree in a related field; experience with Ansys HFSS, Keysight ADS, VNA/TDR/oscilloscope; Python and MATLAB proficiency; strong communication and teamwork.
Ansys HFSS, Keysight ADS, VNA, TDR, spectrum analyzer, high-speed oscilloscope, Python, MATLAB, S-parameters, IBIS-AMI
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ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
7+ YOEBachelor’s +7 years, or Master’s +4, or PhD +1; SystemVerilog/UVM; verification methodologies incl. emulation; architecture and leadership in verification; scripting (Python, Perl) and C/C++.
SystemVerilog, UVM, emulation, Python, Perl, C/C++
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Sr. Design Verification Engineer
San Jose, California, United States
$130k-$160k/yr OnsiteFull Time
Credo Semiconductor
Credo SemiconductorNASDAQ: CRDO: Designing high-speed semiconductor connectivity solutions for data infrastructure.
7+ YOEBS/MS in EE/CE, 7+ years RTL/functional verification using SV/UVM, PCIe and gate-level experience, firmware-based simulation and C knowledge, strong debugging and scripting (Python/Perl/Shell) skills.
SV, UVM, C, Python, Perl, Shell scripting, PILOT
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Sr. Staff ASIC Verification Engineer
Sunnyvale or San Jose or Munich
OnsiteFull Time
Tensordyne
Tensordyne: Designs AI chips and systems for efficient model inference.
15+ YOE15+ years ASIC verification experience; expert in SystemVerilog and UVM; experience with SoC/subsystem verification, ARM/RISC-V, high-speed interfaces, C/C++/SystemC; scripting with Python/Perl/Tcl/Shell; BS required, MS preferred.
SystemVerilog, UVM, C, C++, SystemC, Python, Perl, Tcl, Shell
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1mo
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
Viasat
ViasatNASDAQ: VSAT: Provider of global satellite-based connectivity and secure communication solutions.
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
Ayar Labs
Ayar Labs: Develops optical interconnect technology for high-speed data movement.
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
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3w
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Senior Staff Engineer, GPU Design Verification (Formal Verification)
San Jose, California, United States
$198k-$297k/yr OnsiteFull Time
Samsung Electronics
Samsung ElectronicsKorea Exchange: 005930: Develops and manufactures consumer electronics, semiconductors, and mobile devices.
8+ YOE8+ years verification experience (formal verification focus), proficiency in formal methods, System Verilog/SVA, Python/Perl/C++, EDA formal tools, strong debugging and architecture knowledge; BS/MS/PhD in CS/CE/related.
Python, Perl, C/C++, System Verilog, System Verilog Assertions (SVA), Confluence, JIRA, Universal Verification Methodology (UVM), UPF
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3mo
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Integration and Verification Engineer, Turbogenerator
San Jose, California, United States
$172k-$216k/yr OnsiteFull Time
Archer
ArcherNYSE: ACHR: Develops electric vertical takeoff and landing aircraft for urban mobility.
10+ YOEBS/MS/PhD in a related scientific or engineering field; 10+ years in complex system verification; strong systems engineering; experience with turbine and/or electrical systems; ability to meet tight timelines; excellent communication; independent leadership.
Test benches, LabVIEW, Matlab/Simulink, Systems verification, Aerospace testing
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