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28 asic engineer jobs at 7 companies in Davis, CA

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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
5+ YOEBachelor’s in Electrical Engineering; 5+ years ASIC design experience; strong Verilog/SystemVerilog; timing/room for leadership; knowledge of EDA tools; Python/Perl a plus.
Verilog, SystemVerilog, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
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Staff/Principal Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
6+ YOEB.S. in EE/CS or equivalent, 6+ years verification experience, RTL debugging, scoreboarding, code coverage analysis, test-plan development; System-Verilog/UVM expertise preferred; familiarity with C and emulation advantageous.
System-Verilog, UVM, C, Claude-Code, RTL
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3mo
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Technical Staff Engineer - Emulation
San Jose or Roseville
$91k-$232k/yr OnsiteFull Time
Microchip Technology
Microchip TechnologyNasdaq: MCHP: Manufacturer of microcontrollers, analog, and mixed-signal integrated circuits.
12+ YOEBachelor's in Electrical or Computer Engineering; 12+ years in ASIC development and emulation; strong problem solving and communication; experience with PCIe, Cadence Palladium/Protium; UVM testbenches; SoC emulation expertise.
Cadence Palladium, Cadence Protium, PCIe, DDR, ONFI, AMBA AXI, SAS, NVMe, UVM, BFM, C
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
Solidigm
Solidigm: Develops and manufactures NAND flash memory and solid-state drives.
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
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Senior Technologist, Hardware Development Engineering -
Roseville, California, United States
$177k-$235k/yr OnsiteFull Time
Western Digital
Western DigitalNASDAQ: WDC: Design and manufacture data storage devices and systems.
Expert-level hardware engineer with hands-on board and ASIC integration experience, high-speed interface and SI/PI expertise, lab bring-up and root-cause debug, and cross-functional technical leadership.
Cadence, Altium, Mentor, IBIS, AMI, S-parameters, SPICE, Oscilloscope, BERT, Network Analyzer, Spectrum Analyzer, JTAG, PRBS, IBERT
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Senior SoC Network Subsystem Architect
Santa Clara or Hillsboro or Folsom or Austin or Phoenix or San Jose
$164k-$269k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
7+ YOEBachelor's in EE/CE/CS and 7+ years building networking ASIC/SoC/IPU/DPU architectures, high-speed packet processing pipelines, and system-level tradeoffs; experience with programmable datapaths (P4) preferred.
P4
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
Aptiv
AptivNYSE: APTV: Engineers electrical architectures and safety software for vehicles.
12+ YOEBachelor's in EE/CE,12+ years ARM CPU SoC/ASIC architecture experience, Ethernet/PCIe and memory subsystem expertise, EM/thermal tradeoff and IP selection experience, scripting in Tcl/Perl/Python preferred.
Tcl, Perl, Python
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